Siemens announced the partnership expansion on July 26, during the Design Automation Conference in San Francisco. It's the latest move in a multi-year EDA buying spree for the German industrial giant — just the week before, it had acquired Defacto Technologies and Precision Innovations in back-to-back deals. The NVIDIA collaboration sits on top of that foundation, layering AI reasoning on software that already dominates substantial portions of the chip design flow.
The timing matters because EDA workflows are hitting a complexity wall. Advanced nodes, chiplets, and 3D-IC integration have made design verification the dominant bottleneck — it now consumes up to 70 % of total chip design effort, according to Siemens' own numbers. More designers and bigger teams don't scale linearly against a combinatorial explosion of test scenarios. That's the problem this announcement is aimed at.
What "self-verifying" actually means
The term sounds like marketing, but there's a concrete engineering idea underneath. The Fuse EDA AI Agent system — introduced earlier this year — can now coordinate multiple AI agents across design stages. The difference with this update is that those agents continuously validate their output against deterministic EDA engines. Think of it less as "AI does the design" and more as "AI proposes, then the physics-based simulator says yes or no, and the AI learns from the answer."
The NVIDIA side supplies four pieces: NeMo Gym (a library for building agentic environments), Nemotron models (for reasoning), OpenShell (a secure runtime with access controls and audit trails), and CUDA-X accelerated computing. The OpenShell component is particularly worth noting for European customers — it provides enterprise-grade security for running autonomous agents across design environments, with governed runtime guardrails. For EU-based semiconductor firms subject to the AI Act's high-risk classification for critical infrastructure tools, having an auditable agent runtime is not optional.
The system also plugs into Siemens' recently launched Intelligence Center X, an industrial AI platform that coordinates agents across design, manufacturing, and supply chain — essentially connecting chip design to broader enterprise workflows.
Where the numbers land: Solido Characterization Suite
Here's where Siemens gets specific. The Solido Characterization Suite — used for generating and verifying Liberty-format files for standard cell, memory, and custom IP libraries at advanced nodes — now runs with agentic AI orchestration. The claimed improvements:
- More than 10× reduction in characterization turnaround time
- 5–10× reduction in token costs compared to previous AI-assisted approaches
The second number is the interesting one. Most coverage of this announcement focuses on speed, but the cost efficiency matters more for production workflows that run continuously. EDA tool licensing is already expensive — adding AI on top with per-token pricing could make it worse, not better. Siemens is explicitly claiming the opposite: that the agentic orchestration makes AI usage cheaper per run, not just faster. That's a practical claim that customers will verify quickly once the software ships.
Solido Layout Analyzer: natural language meets parasitic extraction
The other concrete new product is Solido Layout Analyzer, a tool for post-layout parasitic and layout-dependent-effect analysis. Its headline feature: you can ask questions about your layout in plain English and get analysis, fixing recommendations, and generated reports.
STMicroelectronics — the Franco-Italian semiconductor company and a major European chipmaker — has already gone on the record with a specific use case. Gianbattista Lo Giudice, Non-Volatile Memory Design manager at ST, said the Layout Analyzer helps his team "relate layout insight directly to electrical behavior" and could "cut down the time we spend debugging complex design blocks by weeks." That's not an abstract claim — it's a named European customer with a measurable time saving.
For context: STMicroelectronics is exactly the kind of company the EU Chips Act was designed to support. The legislation, adopted in 2023, aims to double Europe's share of global semiconductor production to 20 % by 2030. Better design tools — with faster, more reliable verification — are a less visible but equally critical part of that puzzle. You can fab chips anywhere, but if the design tools are all American, the sovereignty goal is incomplete.
The verification elephant and Nemotron 3 Ultra
Siemens is also extending its Questa One Agentic Toolkit with NVIDIA's Nemotron 3 Ultra reasoning model, specifically targeting digital verification. Siemens claims Nemotron 3 Ultra leads among open models in agentic RTL benchmarking with the ACE-RTL agent — a detail that matters because open-weight models avoid vendor lock-in for the underlying reasoning engine.
Abhi Kolpekwar, SVP of Digital Verification Technologies at Siemens EDA, framed it bluntly: "We're at an inflection point where the complexity of AI chips, chiplets, and 3D ICs has outpaced traditional verification methodologies." He added that agents can now "reason across billions of test scenarios, and deliver production-quality results in timeframes that were impossible just two years ago."
Whether you read that as engineering enthusiasm or marketing, the underlying dynamic is real. When we benchmark AI models in our own testing, reasoning quality and tool-calling reliability are the two factors that determine whether an agent is genuinely useful or just an expensive demo. Siemens's bet — and NVIDIA's — is that combining domain-specific EDA engines with general-purpose reasoning models produces better results than either could achieve alone.
A European EDA heavyweight getting heavier
Siemens is not new to EDA. The company entered the market through its acquisition of Mentor Graphics in 2017 and has been expanding steadily since. With the recent Defacto Technologies and Precision Innovations acquisitions, plus the NVIDIA partnership, Siemens Digital Industries Software — a 70,000-employee division within the broader €78.9-billion-revenue Siemens Group — is positioning itself as a full-stack alternative to Synopsys and Cadence.
The European semiconductor ecosystem stands to gain. Companies like Infineon (Germany), NXP (Netherlands), Bosch (Germany), and STMicroelectronics all use these tools, and having a European-headquartered EDA vendor with deep AI capability reduces dependence on US-only supply chains. The EU AI Act classification of AI-assisted design tools remains an open question — the European Commission has not yet issued specific guidance for EDA software using large language models — but Siemens being under EU jurisdiction simplifies compliance compared to routing sensitive design data through US-based AI services.
Timothy Costa, NVIDIA's VP of computational engineering, summed up the partnership's scope: "Semiconductor and PCB design are among the most complex engineering challenges in the world, and AI agents need trusted tools to reason, act and verify their work." The trust part is key — and it's also where European regulation will have the most to say.
What ships, what doesn't, and what to watch
The capabilities are listed as "available in forthcoming releases" — no fixed date, which is normal for EDA vendor announcements. The technology spans Siemens' full EDA portfolio: Catapult (high-level synthesis), Questa One and Veloce (verification), Solido (custom IC), Aprisa (physical implementation), Calibre (signoff), Tessent (design-for-test), Innovator3D IC (3D integration), and Xpedition (PCB design). That's comprehensive, but it also means the actual quality of the AI experience will vary across tools — some are natural fits for agentic orchestration (verification, characterisation), while others may see more modest gains initially.
For engineering teams in Europe, the practical takeaway is straightforward: if you're already in the Siemens EDA ecosystem, these capabilities are coming at no extra partnership announcement cost, though licensing details remain undisclosed. If you're evaluating EDA vendors, the self-verifying agent angle is a differentiator worth testing against comparable offerings from Synopsys (which has its own Synopsys.ai suite) and Cadence.
Is Siemens replacing human chip designers with AI?
No. The announcement describes AI agents that assist, propose, and verify — but every decision is ultimately validated against physics-based EDA engines. The human engineer remains in the loop for design direction and signoff. The goal is to automate the repetitive parts of verification and characterization, not to replace design expertise.
How does this relate to the EU AI Act?
AI-assisted EDA tools used in critical infrastructure (semiconductor design) could fall under the AI Act's high-risk classification. Siemens' use of the OpenShell secure runtime with audit trails and governed access controls appears designed to address these requirements. However, the European Commission has not yet issued sector-specific guidance for AI in EDA, so the exact compliance pathway remains to be defined.
What does this mean for token costs in chip design workflows?
Siemens claims 5–10× lower token costs for Solido characterization compared to previous AI-assisted methods. If those numbers hold in production, it matters — EDA AI workflows can run continuously for days, and per-token pricing adds up. The efficiency gain comes from better agent orchestration that reduces redundant context and focuses reasoning on productive tasks.
Will this work with non-NVIDIA hardware?
The announcement is NVIDIA-specific, covering NeMo Gym, Nemotron models, and CUDA-X. Siemens has not disclosed whether alternative backends are planned. For European companies concerned about hardware vendor diversity — particularly given the EU's push for chip sovereignty — this is a question worth raising with Siemens directly.
